The present invention relates to memory hardware, and more particularly, to a semiconductor memory device for improving the transmission data rate of a data input and output bus, and a memory module including such a device.
Memory modules are circuit boards designed to mount memory chips. Generally, memory modules are easily inserted into and extracted from a connector within the computer system. Memory modules are driven by being connected to all necessary power sources, ground power sources, and logic signals.
Memory modules typically include a plurality of RAM chips mounted on a print circuit board. DRAM, SRAM, or video RAM can be used in various applications depending on the requirements. DRAMs are generally cheaper and have a larger capacity than SRAMs, so that they have been widely used as essential elements such as the main memory of computer systems. SRAM and video RAM modules are more restricted in use and so they are respectively applied to special purposes such as for a cache memory or for a video frame buffer.
Many techniques are used for fast operation of a DRAM. For example, fast access modes such as page mode, a static column mode, and a nibble mode are used. Characteristics such as enhanced DRAMs or RAMBUS DRAMs are also used. Accordingly, memory modules using various different RAM memories are required to improve the bandwidth of a memory, i.e., the speed of information that can be exchanged with a memory.
The appearance of synchronous DRAMs (SDRAMs) is one of the newest and the most important improvements in the area of memory access speed and bandwidth. SDRAMs are different from asynchronous DRAMs in that they operate in synchronization with a clock signal. Typically, SDRAMs have predetermined sections where data read from a memory is effective. Data is essentially read in response to a clock signal combined with a read command provided to SDRAMs. In other words, SDRAMs output the effective data of a memory cell after a read command is issued, and maintain the data throughout a predetermined period. This predetermined period is called "valid data window." Thus, the SDRAMs provide data within the valid data window in accordance with a continuous clock signal. A method of reading data from a module including an SDRAM has been disclosed in U.S. Pat. No. 5,577,236, the contents of which are hereby incorporated by reference in their entirety.
According to this U.S. patent, when data is read from a memory bank of an SDRAM, a memory controller provides an optimal clock signal to compensate for the delay of read data due to a line load and a process variation upon manufacture of chips and cards. SDRAMs perform reading/writing operations in accordance with the rising edge of the optimal clock signal. This means that memory cell data is read from an SDRAM and transferred to a data input and output bus during one cycle of a clock signal provided to the SDRAM.
As a result, the transmission data rate of the data input and output bus is defined by a clock cycle in the U.S. Pat. No. 5,577,236. In other words, the transmission data rate of the data input and output bus is determined according to the operation of a single data rate SDRAM (SDR SDRAM). Therefore, the transmission data rate described above is not sufficient to satisfy the operation of a memory module that requires a data input and output bus having a high data rate.